Posts

• Acme Text Editor: LSP Tool Support Sep 25
• Fast and Correct Load Link/Store Conditional Instruction Handling in DBT Systems (CASES) Aug 27

• Talk - ARC Processor Summit 2019 Sep 19
• Mitigating JIT Compilation Latency in Virtual Execution Environments (VEE) Apr 14

• First Google and now Facebook use our Concurrent JIT Compilation scheme published at PLDI'11 May 9
• Speed, Accuracy, and Visibility - Instruction Set Simulation without compromise! Apr 27

• nSIM - DesignWare ARC Processor Models Apr 27

• nSIM - Turning research into a product Oct 27
• Speeding up dynamic compilation: concurrent and parallel dynamic compilation (PhD) Jul 2

• Research Impact of Pasta Project Dec 1
• Talk - Euro LLVM Conference 2012 Jun 4
• Efficiently Parallelizing Instruction Set Simulation (LCTES) May 1
• ArcSim - Flexible Ultra-High Speed Instruction Set Simulator Project Jan 1

• Scalable Multi Core Simulation Using Parallel Dynamic Binary Translation (IC-SAMOS) Oct 17

• Cycle Accurate Performance Modelling (IC-SAMOS) Jun 19
• EnCore Castle Processor Fully Functional Jun 10
• Integrated Instruction Selection and Register Allocation for Compact Code Generation (CGO) Apr 1

• PASTA - Processor Automated Synthesis by iTerative Analysis Project Jan 1

• HBURG - Haskell Bottom Up Rewrite Generator Jan 1

• Automatic Code Generation using Dynamic Programming Techniques (MSc) Oct 1

• PortBrowser - A user interface for the BSD ports system Nov 10